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Start of funding 01.07.2005
Design Space Exploration and Buffer Optimization Strategies for Dynamically Reconfigurable Hardware Targets
Prof. Dr.-Ing. Jürgen Teich
Friedrich-Alexander-University of Erlangen-Nuremberg
Lehrstuhl für Informatik 12, Hardware-Software-Co-Design
Dr. Kees Vissers
Xilinx Research Laboratories
Standard
The well-known productivity gap between Semiconductor technology and required tool support (electronic design automation) must be bridged in order to develop so-called “Systems-on-a-Chip” in time, correctly and with proven efficiency regarding performance, power as well as cost and area requirements.
For achieving this goal, Xilinx Research is investigating block-oriented design models and languages and the automization of mapping complex applications such as digital signal and image processing algorithms onto FPGA-based reconfigurable hardware targets.
In this area, we will investigate how to include a) design space exploration and b) buffer analysis and optimization techniques into the design-flow. The final goal is to propose alternative tradeoffs early in the design with considerably less buffer memory requirements.
Final report:
The Co-Design framework SystemCoDesigner as developed in Erlangen
was extended by a frontend compiler that may translate actor-based system-level
specifications specified in the language CAL into SystemC descriptions that are
used in order to perform a timing analysis and design space exploration.
The compiler was implemented in XSLT, a language for transformations of XML documents,
and verified on examples of signal processing applications ranging from simple filters
to complex and hierarchical blocks. Subsequently, automatic design space exploration
was applied. Through the synthesis of concrete design points for FPGA targets,
consisting of a combination of communicating processors and synthesized hardware
blocks, a calibration of cost and timing functions was achieved.
The stay with Xilinx has built the foundation of an ongoing active scientific exchange
with several individuals at Xilinx, California.